1. Field of the Invention
The present invention relates to a method for producing a Group III nitride semiconductor light-emitting device exhibiting improved light extraction efficiency by using a textured sapphire substrate.
2. Background Art
Recently, Group III nitride semiconductor light-emitting devices have been used for general lighting purposes, and improvement of light extraction efficiency is strongly demanded. One of the well-known methods for improving light extraction efficiency is to texture a sapphire substrate having a c-plane main surface, as is disclosed in Japanese Patent Application Laid-Open (kokai) No. 2003-318441 or 2007-19318. When the sapphire substrate is flat without texturing, a light propagating in a direction horizontal to the sapphire substrate inside an element, is confined in a semiconductor layer and attenuated due to repeated multiple reflection. However, the light propagating in a horizontal direction can be emitted outside through reflection and scattering in a vertical direction by providing a texture on the sapphire substrate, resulting in improvement of light extraction efficiency.
One conceivable approach to further improve light extraction efficiency is to increase the texture depth of the sapphire substrate. However, when the texture depth is increased, a large pit is generated on a region where dislocations are concentrated due to bending of dislocation. Such large pit causes the deterioration of the electrical characteristics of the device, for example, the reduction of the electrostatic breakdown voltage.
In addition, to sufficiently improve light extraction efficiency, preferably the depth of the texture on the sapphire substrate is increased, and the inclination angle of a side surface of the texture (the angle of the side surface of the concave portion or the side surface of the convex portion with respect to the main surface of the sapphire substrate) falls within a range of 40° to 80°. However, such approach increases the regions that are not the c-plane on the sapphire substrate, leading to generation of pits on the crystal surface or uneven crystallinity. This results in the deterioration of the electrical characteristics of the device, for example, the reduction of the electrostatic breakdown voltage.
Studies by the present inventors have shown that the pit is generated due to mass transport of a buffer layer. When the temperature increases to the temperature at which an n-contact layer is formed after the formation of the buffer layer on the sapphire substrate, the buffer layer is moved to the c-plane of the sapphire substrate through mass transport. Thus, a region without the buffer layer is generated on the sapphire substrate. Since there are both regions with and without the buffer layer as the seeds of crystal growth, crystal defects are concentrated in the region without the buffer layer, and a pit is generated therein, resulting in the deterioration of the electrical characteristics, for example, the reduction of the electrostatic breakdown voltage.